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general description the ds1921g thermochron i button is a rugged, self- sufficient system that measures temperature and records the result in a protected memory section. the recording is done at a user-defined rate, both as a direct storage of temperature values as well as in the form of a histogram. up to 2048 temperature values taken at equidistant inter- vals ranging from 1 to 255min can be stored. the his- togram provides 63 data bins with a resolution of 2.0?. if the temperature leaves a user-programmable range, the ds1921g also records when this happened, for how long the temperature stayed outside the permitted range, and if the temperature was too high or too low. an addi- tional 512 bytes of battery-backed sram allow storing information pertaining to the object to which the ds1921g is associated. data is transferred serially through the 1-wire protocol, which requires only a sin- gle data lead and a ground return. every ds1921g is factory lasered with a guaranteed unique, electrically readable, 64-bit registration number that allows for abso- lute traceability. the durable stainless steel package is highly resistant to environmental hazards such as dirt, moisture, and shock. accessories permit the ds1921g to be mounted on almost any object including contain- ers, pallets, and bags. applications features digital thermometer measures temperature in 0.5? increments accuracy ?? from -30? to +70? (see the electrical characteristics for accuracy specification) built-in real-time clock (rtc) and timer has accuracy of ? minutes per month from 0? to +45? water resistant or waterproof if placed inside ds9107 i button capsule (exceeds water resistant 3 atm requirements) automatically wakes up and measures temperature at user-programmable intervals from 1 minute to 255 minutes logs consecutive temperature measurements in 2kb of data-log memory records a long-term temperature histogram with 2.0? resolution programmable temperature high and temperature low alarm trip points records up to 24 timestamps and durations when temperature leaves the range specified by the trip points 512 bytes of general-purpose battery-backed sram communicates to host with a single digital signal at 15.4kbps or 125kbps using 1-wire protocol common i button features digital identification and information by momentary contact unique, factory-lasered, and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike multidrop controller for 1-wire net chip-based data carrier compactly stores information data can be accessed while affixed to object button shape is self-aligning with cup-shaped probes durable stainless-steel case engraved with registration number withstands harsh environments easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim presence detector acknowledges when reader first applies voltage meets ul 913, 5th ed., rev. 1997-02-24; intrinsically safe apparatus: approved under entity concept for use in class i, division 1, group a, b, c, and d locations ds1921g thermochron i button ________________________________________________________________ maxim integrated products 1 ordering information 19-5101; rev 6; 3/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package ds1921g-f5# -40c to +85c f5 i button DS1921G-F5N# -40c to +85c f5 i button examples of accessories part accessory ds9096p self-stick adhesive pad ds9101 multipurpose clip ds9093ra mounting lock ring ds9093a snap-in fob ds9092 i button probe pin configuration appears at end of data sheet. thermochron, i button, and 1-wire are registered trademarks of maxim integrated products, inc. #denotes a rohs-compliant device that may include lead(pb) that is exempt under the rohs requirements. a nist traceability certificate is available for the DS1921G-F5N. see application note 4629 for details. temperature logging in cold chain, food safety, pharmaceutical, and medical products
ds1921g thermochron i button 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v pup = +2.8v to +5.25v, t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. io voltage range relative to gnd ..........................-0.5v to +6v io sink current....................................................................20ma operating temperature range ..........................-40? to +85?* storage temperature range..............................-40? to +50?* parameter symbol conditions min typ max units io pin: general data 1-wire pullup resistance r pup (notes 1, 2) 2.2 k input capacitance c io (notes 3, 4) 100 800 pf input load current i l io pin at v pup (note 5) 10 a v pup > 4.5v 1.14 2.70 high-to-low switching threshold (notes 4, 6, 7, 8) v tl 0.71 2.70 v input low voltage v il (notes 1, 6, 9) 0.30 v v pup > 4.5v 1.00 2.70 low-to-high switching threshold (notes 4, 6, 7, 10) v th 0.66 2.70 v output low voltage at 4ma v ol (notes 6, 11) 0.4 v standard speed, r pup = 2.2k 5 overdrive speed, r pup = 2.2k 2 recovery time (notes 1, 4) t rec overdrive speed, directly prior to reset pulse; r pup = 2.2k 5 s standard speed 65 time-slot duration (notes 1, 12) t slot overdrive speed 8 s io pin: 1-wire reset, presence-detect cycle standard speed, v pup > 4.5v 480 640 standard speed 540 640 overdrive speed, v pup > 4.5v 48 80 reset low time (notes 1,12) t rstl overdrive speed 58 80 s standard speed 15 60 presence-detect high time (note 12) t pdh overdrive speed 1.1 6 s standard speed 60 270 overdrive speed, v pup > 4.5v 7.5 24 presence-detect low time (note 12) t pdl overdrive speed 7.5 32 s standard speed 60 75 presence-detect sample time (notes 1, 4) t msp overdrive speed 6 8.6 s * storage or operation above +50? significantly reduces battery life.
ds1921g thermochron i button _______________________________________________________________________________________ 3 note 1: system requirement. note 2: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2480b may be required. note 3: capacitance on io could be 800pf when power is first applied. if a 2.2k ? resistor is used to pull up the data line, 2.5? after v pup has been applied, the parasite capacitor does not affect normal communication. note 4: these values are derived from simulation across process, voltage, and temperature and are not production tested. note 5: input load is to ground. note 6: all voltages are referenced to ground. note 7: v tl and v th are functions of the internal supply voltage, which is a function of v pup and the 1-wire recovery times. the v th and v tl maximum specifications are valid at v pup = 5.25v. in any case, v tl < v th < v pup . note 8: voltage below which, during a falling edge of io, a logic 0 is detected. note 9: the voltage on io must be less than or equal to v ilmax whenever the master drives the line low. note 10: voltage above which, during a rising edge on io, a logic 1 is detected. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: numbers in bold are not in compliance with the published i button standards. see the comparison table . note 13: in figure 15 represents the time required for the pullup circuitry to pull the voltage on the io pin up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 14: in figure 15 represents the time required for the pullup circuitry to pull the voltage on the io pin up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 15: this number was derived from a test conducted by cemagref in antony, france, in july 2000. http://www.cemagref.fr/english/index.htm test report no. e42 note 16: total accuracy is ? ? plus 0.25? quantization due to the 0.5? digital resolution of the device. electrical characteristics (continued) (v pup = +2.8v to +5.25v, t a = -40? to +85?.) parameter symbol conditions min typ max units io pin: 1-wire write standard speed 60 120 overdrive speed, v pup > 4.5v 6 15 write-zero low time (notes 1, 12, 13) t w0l overdrive speed 8.5 15 s standard speed 5 15 write-one low time (notes 1, 13) t w1l overdrive speed 1 2 s io pin: 1-wire read standard speed 5 15 - read low time (notes 1, 14) t rl overdrive speed 1 2 - s standard speed t rl + 15 read sample time (notes 1, 14) t msr overdrive speed t rl + 2 s real-time clock frequency deviation f -5c to +46c -48 +46 ppm temperature converter tempcore operating range t tc -40 +85 c conversion time t conv 19 90 ms thermal response time constant resp (note 15) 130 s -40c to < -30c -1.3 +1.3 -30c to +70c -1.0 +1.0 conversion error (notes 16, 17) > +70c to +85c -1.3 +1.3 c number of conversions n conv (notes 4, 18) (see the lifetime graphs.)
ds1921g note 17: warning: not for use as the sole method of measuring or tracking temperature in products and articles that could affect the health or safety of persons, plants, animals, or other living organisms, including but not limited to foods, beverages, pharmaceuticals, medications, blood and blood products, organs, flammable, and combustible products. user shall assure that redundant (or other primary) methods of testing and determining the handling methods, quality, and fitness of the articles and products should be implemented. temperature tracking with this product, where the health or safety of the aforementioned persons or things could be adversely affected, is only recommended when supplemental or redundant information sources are used. data-logger products are 100% tested and calibrated at time of manufacture by maxim to ensure that they meet all data sheet parameters, including temperature accuracy. user shall be responsible for proper use and storage of this product. as with any sensor-based product, user shall also be responsible for occasionally rechecking the temperature accuracy of the product to ensure it is still operating properly. note 18: the number of temperature conversions (= samples) possible with the built-in energy source depends on the operating and storage temperature of the device. when not in use for a mission, the rtc oscillator should be turned off and the device should be stored at a temperature not exceeding +25?. under this condition the shelf life time is 10 years minimum. thermochron i button 4 _______________________________________________________________________________________ comparison table legacy values ds1921g values standard speed (s) overdrive speed (s) st andard speed (s) overdrive speed (s) parameter min max min max min max min max t slot (including t rec ) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined) t rstl 480 (undefined) 48 80 540 640 58 80 t pdh 15 60 2 6 15 60 1.1 6 t pdl 60 240 8 24 60 270 7.5 32 t w0l 60 120 6 16 60 120 8.5 15 i button can physical specification size see the package information section. weight ca. 3.3g safety meets ul 913, 5th ed., rev. 1997-02-24; intrinsically safe apparatus, approval under entity concept for use in class i, division 1, group a, b, c, and d locations. * intentional change; longer recovery time between time slots. note: numbers in bold are not in compliance with the published i button standards. electrical characteristics (continued) (v pup = +2.8v to +5.25v, t a = -40? to +85?.)
ds1921g thermochron i button _______________________________________________________________________________________ 5 rtc deviation vs. temperature -10 -8 -6 -4 -2 0 2 4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ( c) rtc deviation (minutes/month) upper limit lower limit minimum product lifetime vs. temperature at different sample rates 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 minimum product lifetime (years) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ( c) every minute every 3 minutes every 10 minutes no samples oscillator off
ds1921g thermochron i button 6 _______________________________________________________________________________________ minimum product lifetime vs. sample rate at different temperatures 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 1 10 100 1000 minutes between samples minimum product lifetime (years) +15 c +40 c +60 c +70 c +85 c +45 c +50 c +55 c -20 c -40 c accuracy limits -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 accuracy ( c) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ( c) upper limit lower limit
detailed description the ds1921g thermochron i button is an ideal device to monitor the temperature of any object it is attached to or shipped with, such as perishable goods or con- tainers of temperature-sensitive chemicals. the gener- al-purpose battery-backed sram can store an electronic copy of shipping information, date of manu- facture and other important data written as clear as well as encrypted files. note that the initial sealing level of the ds1921g achieves ip56. aging and use conditions can degrade the integrity of the seal over time, there- fore, for applications with significant exposure to liq- uids, sprays, or other similar environments, it is recommended to place the thermochron in the ds9107 i button capsule. the ds9107 provides a watertight enclosure that has been rated to ip68 (refer to application note 4126: understanding the ip (ingress protection) ratings of i button data loggers and capsule ). overview figure 1 shows the relationships between the major control and memory sections of the ds1921g. the device has seven main data components: 64-bit lasered rom; 256-bit scratchpad; 4096-bit general- purpose sram; 256-bit register page of timekeeping, control, and counter registers; 96 bytes of alarm time- stamp and duration logging memory; 126 bytes of ds1921g thermochron i button _______________________________________________________________________________________ 7 general-purpose sram alarm timestamp and duration logging memory register page memory function control 64-bit lasered rom 256-bit scratchpad control logic 32.768khz oscillator 3v lithium io temperature core data-log memory internal timekeeping, control registers, and counters histogram memory rom function control 1-wire port parasite-powered circuitry ds1921g figure 1. block diagram
ds1921g thermochron i button 8 _______________________________________________________________________________________ available commands: command codes: data field affected: read rom match rom search rom skip rom overdrive-skip rom overdrive-match rom conditional search rom 33h 55h f0h cch 3ch 69h ech 64-bit rom 64-bit rom 64-bit rom n/a od-flag 64-bit rom, od-flag 64-bit rom, conditional search settings, device status 1-wire rom function commands write scratchpad read scratchpad copy scratchpad read memory read memory wth crc clear memory convert temperature 0fh aah 55h f0h a5h 3ch 44h 256-bit scratchpad, flags 256-bit scratchpad 4096-bit sram, registers, flags all memory all memory mission timestamp, mission samples counter, start delay, sample rate, alarm timestamps and durations, histogram memory memory address 211h ds1921g-specific memory/control function commands command level: bus master 1-wire net other devices ds1921g figure 2. hierarchical structure for 1-wire protocol histogram memory; and 2048 bytes of data-log mem- ory. except for the rom and the scratchpad, all other memory is arranged in a single linear address space. all memory reserved for logging purposes, including counter registers and several other registers, is read- only for the user. the timekeeping and control regis- ters are write protected while the device is programmed for a mission. the hierarchical structure of the 1-wire protocol is shown in figure 2. the bus master must first provide one of the seven rom function commands: read rom, match rom, search rom, conditional search rom, skip rom, overdrive-skip rom, or overdrive-match rom. upon completion of an overdrive rom com- mand byte executed at standard speed, the device enters overdrive mode, where all subsequent communi- cation occurs at a higher speed. the protocol required for these rom function commands is described in figure 13. after a rom function command is success- fully executed, the memory functions become accessi- ble and the master can provide any one of the seven available commands. the protocol for these memory function commands is described in figure 10. all data is read and written least significant bit first. parasite power figure 1 shows the parasite-powered circuitry. this cir- cuitry ?teals?power whenever the io input is high. io provides sufficient power as long as the specified tim- ing and voltage requirements are met. the advantages of parasite power are two-fold: 1) by parasiting off this input, battery power is not consumed for 1-wire rom function commands, and 2) if the battery is exhausted for any reason, the rom may still be read normally. the remaining circuitry of the ds1921g is solely operated by battery energy. as a consequence, if the battery is exhausted, all memory data is lost including the data of the last mission, and no new mission can be started. refer to application note 5057: onewireviewer tips and tricks for how to check the battery status.
ds1921g thermochron i button _______________________________________________________________________________________ 9 msb 8-bit crc code 48-bit serial number msb msb lsb lsb lsb 8-bit family code (21h) msb lsb figure 3. 64-bit lasered rom 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 figure 4. 1-wire crc generator 64-bit lasered rom each ds1921g contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits (see figure 3 for details). the 1-wire crc is generated using a polynomial generator consisting of a shift regis- ter and xor gates as shown in figure 4. the polynomi- al is x 8 + x 5 + x 4 + 1. additional information about the 1-wire crc is available in application note 27: understanding and using cyclic redundancy checks with maxim i button products . the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is then entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc returns the shift register to all zeros. memory figure 5 shows the ds1921g memory map. the 4096-bit general-purpose sram makes up pages 0 to 15. the timekeeping, control, and counter registers fill page 16, called register page (see figure 6). pages 17, 18, and 19 are assigned to storing the alarm timestamps and durations. the temperature histogram bins begin at page 64 and use up to four pages. the data-log memory cov- ers pages 128 to 191. memory pages 20 to 63, 68 to 127, and 192 to 255 are reserved for future extensions. the scratchpad is an additional page that acts as a buffer when writing to the sram or the register page. the memory pages 17 and higher are read only for the user. they are written to or erased solely under the supervision of the on-chip control logic.
ds1921g thermochron i button 10 ______________________________________________________________________________________ 32-byte intermediate storage scratchpad address 0000h to 01ffh general-purpose sram (16 pages) pages 0 to 15 0200h to 021fh 32-byte register page page 16 0220h to 027fh alarm timestamps and durations pages 17 to 19 0280h to 07ffh (reserved for future extensions) pages 20 to 63 0800h to 087fh temperature histogram memory pages 64 to 67 0880h to 0fffh (reserved for future extensions) pages 68 to 127 1000h to 17ffh data-log memory (64 pages) pages128 to 191 1800h to 1fffh (reserved for future extensions) pages 192 to 255 figure 5. memory map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function access* 0200h 0 10 seconds single seconds 0201h 0 10 minutes single minutes 0202h 0 12/24 20 hour am/pm 10 hour single hours 0203h 0 0 0 0 0 day of week 0204h 0 0 10 date single date 0205h cent 0 0 10 months single months 0206h 10 years single years rtc registers r/w r/w** 0207h ms 10 seconds alarm single seconds alarm 0208h mm 10 minutes alarm single minutes alarm 0209h mh 12/24 20 hour am/pm alarm 10 hour alarm single hours alarm 020ah md 0 0 0 0 day of week alarm rtc alarm registers r/w r/w** 020bh temperature low alarm threshold 020ch temperature high alarm threshold temperature alarms r/w r/w** 020dh number of minutes between temperature conversions sample rate r/w r** 020eh eosc emclr 0 em ro tls ths tas control r/w r/w** 020fh (no function, reads 00h) r r** figure 6. register pages map * the left entry in the access column is valid between missions. the right entry shows the applicable access mode while a mission is in progress. ** while a mission is in progress, these addresses can be read. the first attempt to write to these registers (even read-only ones), however, ends the mission and overwrites selected writable registers.
ds1921g thermochron i button ______________________________________________________________________________________ 11 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function access* 0210h (no function, reads 00h) r r** 0211h temperature read-out (forced conversion) temperature r r** 0212h low byte 0213h high byte mission start delay r/w r/w** 0214h tcb memclr mip sip 0 tlf thf taf status r/w r/w 0215h minutes 0216h hours 0217h date 0218h month 0219h year mission timestamp r r 021ah low byte 021bh center byte 021ch high byte mission samples counter r r 021dh low byte 021eh center byte 021fh high byte device samples counter r r figure 6. register pages map (continued) * the left entry in the access column is valid between missions. the right entry shows the applicable access mode while a mission is in progress. ** while a mission is in progress, these addresses can be read. the first attempt to write to these registers (even read-only ones), however, ends the mission and overwrites selected writable registers. detailed register descriptions timekeeping the rtc/alarm and calendar information is accessed by reading/writing the appropriate bytes in the register page, address 0200h to 0206h. note that some bits are set to 0. these bits always read 0 regardless of how they are written. the contents of the time, calendar, and alarm registers are in the binary-coded decimal (bcd) format. rtc/calendar the rtc of the ds1921g can run in either 12hr or 24hr mode. bit 6 of the hours register (address 0202h) is defined as the 12hr or 24hr mode select bit. when high, the 12hr mode is selected. in the 12hr mode, bit 5 is the am/pm bit with logic 1 being pm. in the 24hr mode, bit 5 is the 20hr bit (20hr to 23hr). to distinguish between the days of the week, the ds1921g includes a counter with a range from 1 to 7. the assignment of a counter value to the day of week is arbitrary. typically, the number 1 is assigned to a sunday (u.s. standard) or to a monday (european stan- dard). the calendar logic is designed to automatically com- pensate for leap years. for every year value that is either 00 or a multiple of four, the device adds a 29th of february. this works correctly up to (but not including) the year 2100. the ds1921g is y2k compliant. bit 7 (cent) of the months register at address 0205h serves as a century flag. when the year register rolls over from 99 to 00, the century flag toggles. it is recommended to write the century bit to a 1 when setting the rtc to a time/date between the years 2000 and 2099.
ds1921g rtc alarms the ds1921g also contains an rtc alarm function. the rtc alarm registers are located in registers 0207h to 020ah. the most significant bit of each of the alarm registers is a mask bit. when all the mask bits are logic 0, an alarm occurs once per week when the values stored in timekeeping registers 0200h to 0203h match the values stored in the rtc alarm registers. any alarm sets the timer alarm flag (taf) in the device? status register (address 214h). the bus master can set the search conditions in the control register (address 20eh) to identify devices with timer alarms by means of the conditional search function (see the rom function commands section). thermochron i button 12 ______________________________________________________________________________________ rtc alarm control alarm register mask bits (bit 7 of 0207h to 20ah) ms mm mh md function 1 1 1 1 alarm once per second. 0 1 1 1 alarm when seconds match (once per minute). 0 0 1 1 alarm when minutes and seconds match (once every hour). 0 0 0 1 alarm when hours, minutes, and seconds match (once every day). 0 0 0 0 alarm when day, hours, minutes, and seconds match (once every week). rtc and rtc alarm registers map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0200h 0 10 seconds single seconds 0201h 0 10 minutes single minutes 0202h 0 12/24 20 hour am/pm 10 hour single hours 0203h 0 0 0 0 0 day of week 0204h 0 0 10 date single date 0205h cent 0 0 10 months single months 0206h 10 years single years 0207h ms 10 seconds alarm single seconds alarm 0208h mm 10 minutes alarm single minutes alarm 0209h mh 12/24 20 hour am/pm alarm 10 hour alarm single hours alarm 020ah md 0 0 0 0 day of week alarm
temperature conversion the ds1921g measures temperatures with a resolution of 0.5?. temperature values are represented in a sin- gle byte as an unsigned binary number, which trans- lates into a theoretical range of 128?. the range, however, has been limited to values from 0000 0000 (00h) through 1111 1010 (fah). the codes 01h to f9h are considered valid temperature readings. if a temperature conversion yields a temperature that is out of range, it is recorded as 00h (if too low) or fah (if too high). since out-of-range results are accumulated in histogram bins 0 and 62 (see the temperature logging and histogram section), the data in these bins is of lim- ited value. for this reason the specified temperature range of the ds1921g is considered to begin at code 04h and end at code f7h, which corresponds to his- togram bins 1 to 61. with t[7?] representing the decimal equivalent of a tem- perature reading, the temperature value is calculated as ? (?) = t[7?]/2 - 40.0 this equation is valid for converting temperature read- ings stored in the data-log memory as well as for data read from the forced temperature conversion readout register (address 0211h). to specify the temperature alarm thresholds, this equa- tion needs to be resolved to t[7?] = 2 x ? (?) + 80.0 a value of 23?, for example, thus translates into 126 decimal or 7eh. this corresponds to the binary patterns 0111 1110, which could be written to a temperature alarm register (address 020bh and 020ch, respectively). sample rate the content of the sample rate register (address 020dh) determines how many minutes the temperature conversions are apart from each other during a mission. the sample rate can be any value from 1 to 255, coded as an unsigned 8-bit binary number. if the memory has been cleared (status register bit memclr = 1) and a mission is enabled (control register bit em = 0), writing a nonzero value to the sample rate register starts a mis- sion. for a full description of the correct sequence of steps to start a temperature-logging mission, see the missioning or mission example: prepare and start a new mission sections. ds1921g thermochron i button ______________________________________________________________________________________ 13 temperature alarm register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 020bh temperature low alarm threshold 020ch temperature high alarm threshold sample rate register map addrress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 020dh sample rate
ds1921g control register the ds1921g is set up for its operation by writing appropriate data to its special function registers that are located in the register page. several functions that are controlled by a single bit only are combined into a single byte called the control register (address 020eh). this register can be read and written. if the device is programmed for a mission, writing to the control regis- ter ends the mission and changes the register contents. the functional assignments of the individual bits are explained below. bit 5 has no function. it always reads 0 and cannot be written to 1. bit 7: enable oscillator ( eosc ). this bit controls the crystal oscillator of the rtc. when set to logic 0, the oscillator starts operation. when written to logic 1, the oscillator stops and the device is in a low-power data- retention mode. this bit must be 0 for normal opera- tion. the rtc must have advanced at least 1 second before a mission start is accepted. bit 6: memory clear enable (emclr). this bit needs to be set to logic 1 to enable the clear memory func- tion, which is invoked as a memory function command. the timestamp, histogram memory as well as the mission timestamp, mission samples counter, mission start delay, and sample rate are cleared only if the clear memory command is issued with the next access to the device . the emclr bit returns to 0 as the next memory function command is executed. bit 4: enable mission ( em ). this bit controls whether the ds1921g begins a mission as soon as the sample rate is written. to enable the device for a mission, this bit must be 0. bit 3: rollover enable/disable (ro). this bit controls whether the data-log memory is overwritten with new data or whether data logging is stopped once the mem- ory is filled with data during a mission. setting this bit to a 1 enables the rollover and data logging continues at the beginning, overwriting previously collected data. clearing this bit to 0 disables the rollover and no further temperature values are stored in the data-log memory once it is filled with data. this does not stop the mis- sion. the device continues measuring temperatures and updating the histogram and alarm timestamps and durations. bit 2: temperature low alarm search (tls). if this bit is 1, the device responds to a conditional search rom command if, during a mission, the temperature has reached or is lower than the low temperature threshold stored at address 020bh. bit 1: temperature high alarm search (ths). if this bit is 1, the device responds to a conditional search rom command if, during a mission, the temperature has reached or is higher than the high temperature threshold stored at address 020ch. bit 0: timer alarm search (tas). if this bit is 1, the device responds to a conditional search rom com- mand if, during a mission, a timer alarm has occurred. since a timer alarm cannot be disabled, the taf flag usually reads 1 during a mission. therefore, it is advis- able to set the tas bit to a 0, in most cases. mission start delay counter the content of the mission start delay counter register determines how many minutes the device waits before starting the logging process. the mission start delay value is stored as an unsigned 16-bit integer number at addresses 0212h (low byte) and 0213h (high byte). the maximum delay is 65,535 minutes, equivalent to 45 days, 12 hours, and 15 minutes. for a typical mission, the mission start delay is 0. if a mission is too long for a single ds1921g to store all temperature readings at the selected sample rate, one can use several devices, staggering the mission start delay to record the full period. in this case, the rollover enable (ro) bit in the control register (address 020eh) must be set to 0 to prevent overwriting of the recorded temperature log after the data-log memory is full. see the mission start and logging process section and figure 11 for details. thermochron i button 14 ______________________________________________________________________________________ control register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 020eh eosc emclr 0 em ro tls ths tas
status register the status register holds device status information and alarm flags. the register is located at address 0214h. writing to this register does not necessarily end a mission. the functional assignments of the individual bits are explained below. the bits mip, tlf, thf, and taf can only be written to 0. all other bits are read-only. bit 3 has no function. bit 7: temperature core busy ( tcb ). if this bit reads 0, the ds1921g is currently performing a temperature conversion. this temperature conversion is either self- initiated because of a mission being in progress or initi- ated by a command when a mission is not in progress. the tcb bit goes low just before a conversion starts and returns to high just after the result is latched into the read-out register at address 0211h. bit 6: memory cleared (memclr). if this bit reads 1, the memory pages 17 and higher (alarm timestamps/ durations, temperature histogram, excluding data-log memory), as well as the mission timestamp, mission samples counter, mission start delay, and sample rate have been cleared to 0 from executing a clear memory function command. the memclr bit returns to 0 as soon as writing a nonzero value to the sample rate register starts a new mission, provided that the em bit is also 0. the memory has to be cleared in order for a mission to start. bit 5: mission in progress (mip). if this bit reads 1, the ds1921g has been set up for a mission and this mis- sion is still in progress. a mission is started if the em bit of the control register (address 20eh) is 0 and a nonze- ro value is written to the sample rate register, address 20dh. the mip bit returns from logic 1 to logic 0 when a mission is ended. a mission ends with the first write attempt (copy scratchpad command) to any register in the address range of 200h to 213h. alternatively, a mis- sion can be ended by directly writing to the status reg- ister and setting the mip bit to 0. the mip bit cannot be set to 1 by writing to the status register. bit 4: sample in progress (sip). if this bit reads 1, the ds1921g is currently performing a temperature conver- sion as part of a mission in progress. the mission sam- ples occur on the seconds rollover from 59 to 00. the sip bit changes from 0 to 1 approximately 250ms before the actual temperature conversion begins allow- ing the circuitry of the chip to wake up. a temperature conversion including a wake-up phase takes maximum 875ms. during this time, read accesses to the memory pages 17 and higher are permissible but can reveal invalid data. bit 2: temperature low flag (tlf). logic 1 in the temperature low flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or lower than the value in the temperature low threshold register. the temperature low flag can be cleared at any time by writing this bit to 0. this flag must be cleared before starting a new mission. bit 1: temperature high flag (thf). logic 1 in the temperature high flag bit indicates that a temperature measurement during a mission revealed a temperature equal to or higher than the value in the temperature high threshold register. the temperature high flag can be cleared at any time by writing this bit to 0. this flag must be cleared before starting a new mission. bit 0: timer alarm flag (taf). if this bit reads 1, a rtc alarm has occurred (see the timekeeping section for details). the timer alarm flag can be cleared at any time by writing this bit to logic 0. since the timer alarm cannot be disabled, the taf flag usually reads 1 during a mission. this flag should be cleared before starting a new mission. ds1921g thermochron i button ______________________________________________________________________________________ 15 status register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0214h tcb memclr mip sip 0 tlf thf taf
ds1921g thermochron i button 16 ______________________________________________________________________________________ mission timestamp register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0215h 0 10 minutes single minutes 0216h 0 12/24 20 hour am/pm 10 hour single hours 0217h 0 0 10 date single date 0218h 0 0 0 10 months single months 0219h 10 years single years mission samples counter register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 021ah low byte 021bh center byte 021ch high byte device samples counter register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 021dh low byte 021eh center byte 021fh high byte mission timestamp the mission timestamp register indicates the time and date of the first temperature conversion of a mission. subsequent temperature conversions take place as many minutes apart from each other as specified by the value in the sample rate register. mission samples occur on minute boundaries. mission samples counter the mission samples counter register indicates how many temperature measurements have taken place during the current mission in progress (if mip = 1) or during the latest mission (if mip = 0). the value is stored as an unsigned 24-bit integer number. this counter is reset through the clear memory command. device samples counter the device samples counter register indicates how many temperature measurements have taken place since the device was assembled at the factory. the value is stored as an unsigned, 24-bit integer number. the maximum number that can be represented in this format is 16,777,215, which is higher than the expected lifetime of the ds1921g i button. this counter cannot be reset under software control. temperature logging and histogram once set up for a mission, the ds1921g logs the tem- perature measurements simultaneously byte after byte in the data-log memory as well as in histogram form in the histogram memory. the data-log memory is able to store 2,048 temperature values measured at equidis- tant time points. the first temperature value of a mission is written to address location 1000h of the data-log memory, the second value to address location 1001h and so on. knowing the starting time point (mission timestamp register), the interval between temperature measurements, the mission samples counter register, and the rollover setting, one can reconstruct the time and date of each measurement stored in the data log. there are two alternatives to the way the ds1921g behaves after the 2048 bytes of data-log memory is filled with data. with rollover disabled (ro = 0), the device fills the data-log memory with the first 2048 mis- sion samples. additional mission samples are not logged in the data-log, but the histogram and tempera- ture alarm ram continue to update. with rollover enabled (ro = 1), the data log wraps around and over- writes previous data starting at 1000h for the every 2049th mission sample. in this mode, the device stores the last 2048 mission samples.
for the temperature histogram, the ds1921g provides 63 bins that begin at memory address 0800h. each bin consists of a 16-bit, nonrolling-over binary counter that is incremented each time a temperature value acquired during a mission falls into the range of the bin. the least significant byte of each bin is stored at the lower address. bin 0 begins at memory address 0800h, bin 1 at 0802h, and so on up to 087ch for bin 62, as shown in figure 7. the number of the bin to be updated after a temperature conversion is determined by cutting off the two least significant bits of the binary temperature value. out-of-range values are range locked and count- ed as 00h or fah. since each data bin is 2 bytes, it can increment up to 65,535 times. additional measurements for a bin that has already reached its maximum value are not count- ed; the bin counter remains at its maximum value. with the fastest sample rate of one sample every minute, a 2-byte bin is sufficient for up to 45 days if all tempera- ture readings fall into the same bin. temperature alarm logging for some applications it is essential to not only record temperature over time and the temperature histogram, but also record when exactly the temperature exceed- ed a predefined tolerance band and for how long the temperature stayed outside the desirable range. the ds1921g can log high and low durations. the toler- ance band is specified by means of the temperature alarm threshold registers, addresses 20bh and 20ch in the register page. one can set a high temperature and low temperature threshold. see the temperature conversion section for the data format the temperature has to be written in. as long as the temperature values stay within the tolerance band (i.e., are higher than the low threshold and lower than the high threshold), the ds1921g does not record any temperature alarm. if the temperature during a mission reaches or exceeds either threshold, the ds1921g generates an alarm and sets either the temperature high flag (thf) or the tem- perature low flag (tlf) in the status register (address ds1921g thermochron i button ______________________________________________________________________________________ 17 temperature reading temperature equivalent in c histogram bin number histogram bin address 00h -40.0 or lower 0 800h to 801h 01h -39.5 0 800h to 801h 02h -39.0 0 800h to 801h 03h -38.5 0 800h to 801h 04h -38.0 1 802h to 803h 05h -37.5 1 802h to 803h 06h -37.0 1 802h to 803h 07h -36.5 1 802h to 803h 08h -36.0 2 804h to 805h f3h +81.5 60 878h to 879h f4h +82.0 61 87ah to 87bh f5h +82.5 61 87ah to 87bh f6h +83.0 61 87ah to 87bh f7h +83.5 61 87ah to 87bh f8h +84.0 62 87ch to 87dh f9h +84.5 62 87ch to 87dh fah +85.0 or higher 62 87ch to 87dh figure 7. histogram bin and temperature cross-reference
ds1921g 214h). this way, if the search conditions (address 20eh) are set accordingly, the master can quickly iden- tify devices with temperature alarms by means of the conditional search function (see the rom function commands section). the device also generates a time- stamp of when the alarm occurred and begins record- ing the duration of the alarming temperature. timestamps and durations where the temperature leaves the tolerance band are stored in the address range 0220h to 027fh, as shown in figure 8. this allo- cation allows recording 24 individual alarm events and periods (12 periods for too hot and 12 for too cold). the date and time of each of these periods can be deter- mined from the mission timestamp register and the time distance between each temperature reading. the alarm timestamp is a copy of the mission samples counter register when the alarm first occurred. the least significant byte is stored at the lower address. one address higher than the timestamp, the ds1921g maintains a 1-byte duration counter that stores the number of samples the temperature was found to be beyond the threshold. if this counter has reached its limit after 255 consecutive temperature readings and the temperature has not yet returned to within the toler- ance band, the device issues another timestamp at the next higher alarm location and opens another counter to record the duration. if the temperature returns to nor- mal before the counter has reached its limit, the dura- tion counter of the particular timestamp does not incre- ment any further. should the temperature again cross this threshold, it is recorded at the next available alarm location. this algorithm is implemented for the low tem- perature thresholds as well as for the high temperature threshold. missioning the typical task of the ds1921g i button is recording the temperature of a temperature-sensitive object. before the device can perform this function, it needs to be configured. this procedure is called missioning. first, the ds1921g must have its rtc set to a valid time and date. this reference time can be utc (also called gmt, greenwich mean time) or any other time stan- dard that was chosen for the application. the clock must be running ( eosc = 0) for at least one second. setting an rtc alarm is optional. the memory assigned to store the alarm timestamps and durations, tempera- ture histogram, mission timestamp, mission samples counter, mission start delay, and sample rate must be cleared using the clear memory command. in case there were temperature alarms in the previous mission, the tlf and thf flags need to be cleared manually. to enable the device for a mission, the em flag must be set to 0. these are general settings that have to be made regardless of the type of object to be monitored and the duration of the mission. thermochron i button 18 ______________________________________________________________________________________ address description alarm event 0220h mission samples counter, low byte 0221h mission samples counter, center byte 0222h mission samples counter, high byte 0223h alarm duration counter low alarm 1 0224h to 0227h alarm timestamp and duration low alarm 2 0228h to 024fh alarm timestamp and durations low alarms 3 to 12 0250h mission samples counter, low byte 0251h mission samples counter, center byte 0252h mission samples counter, high byte 0253h alarm duration counter high alarm 1 0254h to 0257h alarm timestamp and duration high alarm 2 0258h to 027fh alarm timestamp and durations high alarms 3 to 12 figure 8. alarm timestamps and durations address map
next, the low temperature and high temperature thresh- olds that specify the temperature tolerance band must be defined. the temperature conversion section describes how to convert a temperature value into the binary code to be written to the threshold registers. the state of the search condition bits in the control register does not affect the mission. if multiple devices are connected to form a 1-wire net, the setting of the search condition enables these devices to participate in the conditional search if certain events, such as timer or temperature alarms, have occurred. details on the search conditions are found in the rom function commands section and in the control regis- ter description. the setting of the rollover-enable bit (ro) and sample rate depends on the duration of the mission and the monitoring requirements. if the most recent temperature history is important, the rollover should be enabled (ro = 1). otherwise, one should estimate the duration of the mission in minutes and divide the number by 2048 to calculate the value of the sample rate (number of minutes between temperature conversions). for example, if the estimated duration of a mission is 10 days (14,400min), then the 2048-byte capacity of the data-log memory would be sufficient to store a new value every 7min. if the ds1921g? data-log memory is not large enough to store all temperature readings, one can use several devices and set the mission start delay to values that make the second device start recording as soon as the memory of the first device is full and so on. the ro bit needs to be set to 0 to disable rollover that would otherwise overwrite the recorded tempera- ture log. after the ro bit and the mission start delay are set, the sample rate register is the last element of data that is written. the sample rate can be any value from 1 to 255, coded as an unsigned 8-bit binary number. as soon as the sample rate is written, the ds1921g sets the mip flag and clears the memclr flag. after as many minutes as specified by the mission start delay are over, the device waits for the next minute boundary, then wakes up, copies the current time and date to the mission timestamp register, and makes the first tem- perature conversion of the mission. this increments both the mission samples counter and device samples counter. all subsequent temperature measurements are taken on minute boundaries specified by the value in the sample rate register. one can read the memory of the ds1921g to watch the mission as it progresses. care should be taken to avoid memory access con- flicts. see the memory access conflicts section for details. address registers and transfer status because of the serial data transfer, the ds1921g employs three address registers, called ta1, ta2, and e/s (figure 9). registers ta1 and ta2 must be loaded with the target address to which the data is written or from which data is sent to the master upon a read com- mand. register e/s acts like a byte counter and transfer status register. it is used to verify data integrity with write commands. therefore, the master has only read access to this register. the lower 5 bits of the e/s regis- ter indicate the address of the last byte that has been written to the scratchpad. this address is called ending offset. bit 5 of the e/s register, called pf or partial byte flag, is set if the number of data bits sent by the master is not an integer multiple of 8. bit 6 is always a 0. note that the lowest 5 bits of the target address also deter- mine the address within the scratchpad where interme- diate storage of data begins. this address is called byte offset. if the target address for a write command is 13ch, for example, then the scratchpad stores incom- ing data beginning at the byte offset 1ch and is full after only 4 bytes. the corresponding ending offset in this example is 1fh. for the best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte off- set is 0. thus, the full 32-byte capacity of the scratch- pad is available, resulting also in the ending offset of 1fh. however, it is possible to write one or several con- tiguous bytes somewhere within a page. the ending offset together with the partial and overflow flag are a means to support the master checking the data integri- ty after a write command. the highest valued bit of the e/s register, called authorization accepted (aa), indi- cates that a valid copy command for the scratchpad has been received and executed. writing data to the scratchpad clears this flag. writing with verification to write data to the ds1921g, the scratchpad must be used as intermediate storage. first, the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. in the next step, the master sends the read scratchpad command to read the scratchpad and to verify data integrity. as preamble to the scratch- pad data, the ds1921g sends the requested target address ta1 and ta2 and the contents of the e/s regis- ter. if the pf flag is set, data did not arrive correctly in the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag indicates that the ds1921g thermochron i button ______________________________________________________________________________________ 19
ds1921g write command was not recognized by the device. if everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. now the master can continue verifying every data bit. after the master has verified the data, it has to send the copy scratchpad command. this command must be followed exactly by the data of the three address registers ta1, ta2, and e/s as the master has read them verifying the scratchpad. as soon as the ds1921g has received these bytes, it copies the data to the requested location beginning at the target address. memory/control function commands the memory/control function flowchart (figure 10) describes the protocols necessary for accessing the memory and the special function registers of the ds1921g. an example on how to use these and other functions to set up the ds1921g for a mission is includ- ed in the mission example: prepare and start a new mission section. the communication between master and ds1921g takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode, the ds1921g assumes standard speed. internal memory access dur- ing a mission has priority over external access through the 1-wire interface. this affects the read memory com- mands described below. see the memory access conflicts section for details. write scratchpad [0fh] after issuing the write scratchpad command, the mas- ter must first provide the 2-byte target address, fol- lowed by the data to be written to the scratchpad. the data is written to the scratchpad starting at the byte off- set t[4:0]. the ending offset e[4:0] is the byte offset at which the master stops writing data. only full data bytes are accepted. if the last data byte is incomplete, its content is ignored and the partial byte flag (pf) is set. when executing the write scratchpad command, the crc generator inside the ds1921g (see figure 16) cal- culates a crc of the entire data stream, starting at the command code and ending at the last data byte sent by the master. this crc is generated using the crc- 16 polynomial by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchpad command, the target addresses ta1 and ta2 as supplied by the master, and all the data bytes. the master can end the write scratchpad command at any time. however, if the ending offset is 11111b, the master can send 16 read time slots and receive an inverted crc-16 generated by the ds1921g. note: the range 200h to 213h of the register page is protected during a mission. see figure 6 for the access type of the individual registers between and during missions. thermochron i button 20 ______________________________________________________________________________________ bit number 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read-only) aa 0 pf e4 e3 e2 e1 e0 figure 9. address registers
read scratchpad [aah] this command is used to verify scratchpad data and target addresses. after issuing the read scratchpad command, the master begins reading. the first 2 bytes are the target address. the next byte is the ending off- set/data status byte (e/s) followed by the scratchpad data beginning at the byte offset t[4:0], as shown in figure 9. regardless of the actual ending offset, the master can read data until the end of the scratchpad after which it receives an inverted crc-16 of the com- mand code, target addresses ta1 and ta2, the e/s byte, and the scratchpad data starting at the target address. after the crc is read, the bus master reads logical ?? from the ds1921g until a reset pulse is issued. copy scratchpad [55h] this command is used to copy data from the scratch- pad to the writable memory sections. applying a copy scratchpad command to the sample rate register can start a mission provided that several preconditions are met. see the mission start and logging process sec- tion and the flowchart in figure 11 for details. after issu- ing the copy scratchpad command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the scratchpad for verification. this pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the aa flag is set and the copy begins. a pattern of alternating ?? and ?? is transmitted after the data has been copied until the master issues a reset pulse. while the copy is in progress, any attempt to reset the part is ignored. copy typically takes 2? per byte. the data to be copied is determined by the three address registers. the scratchpad data from the begin- ning offset through the ending offset is copied, starting at the target address. anywhere from 1 to 32 bytes can be copied to memory with this command. the aa flag remains at logic 1 until it is cleared by the next write scratchpad command. note that the copy scratchpad command, when applied to the address range 200h to 213h during a mission, ends the mission. read memory [f0h] the read memory command can be used to read the entire memory. after issuing the command, the master must provide the 2-byte target address. after the 2 bytes, the master reads data beginning from the target address and can continue until the end of memory, at which point logic ?? are read. it is important to realize that the target address registers contain the address provided. the ending offset/data status byte is unaf- fected. the hardware of the ds1921g provides a means to accomplish error-free writing to the memory section. to safeguard data in the 1-wire environment when read- ing and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. such a packet would typically store a 16-bit crc with each page of data to ensure rapid, error-free data transfers that elim- inate having to read a page multiple times to verify if the received data is correct (refer to application note 114: 1-wire file structure for the recommended file structure). ds1921g thermochron i button ______________________________________________________________________________________ 21
ds1921g thermochron i button 22 ______________________________________________________________________________________ master tx memory or control function command ds1921g sets emclr = 0 master tx data byte to scratchpad offset ds1921g increments scratchpad offset ds1921g sets scratchpad offset = [t4:t0] and clears (pf, aa) 0fh write scratchpad? n y y n y n n y n master tx reset? scratchpad offset = 11111b? master tx reset? master tx reset? master tx ta1 [t7:t0], ta2 [t15:t8] ds1921g sets [e4:e0] = scratchpad offset n from rom functions flowchart (figure 13) to rom functions flowchart (figure 13) y y to figure 10b from figure 10b master rx crc-16 of command, address, data master rx "1"s partial byte written? pf = 1 aa = 1 ds1921g sets emclr = 0 ds1921g sets scratchpad offset = [t4:t0] ds1921g increments scratchpad offset master rx ending offset with data status (e/s) aah read scratchpad? n y y n y n y n master tx reset? scratchpad offset = 11111b? master tx reset? master rx ta1 [t7:t0], ta2 [t15:t8] master rx data byte from scratchpad offset master rx crc-16 of command, address, data, e/s byte, and data starting at the target address master rx "1"s 55h copy scratchpad n y y n n master tx reset? master tx reset? copying finished master tx ta1 [t7:t0], ta2 [t15:t8] ds1921g sets emclr = 0 master tx e/s byte ds1921g copies scratchpad data to memory n y n y y n master tx reset? y authorization code match? ds1921g tx "0" ds1921g tx "1" master rx "1"s master rx "1"s figure 10a. memory/control function flowchart
ds1921g thermochron i button ______________________________________________________________________________________ 23 from figure 10a to figure 10a to figure 10c from figure 10c a5h read memory with crc n y y n master tx reset? crc ok? master tx ta1 [t7:t0], ta2 [t15:t8] ds1921g sets emclr = 0 master rx data byte from memory address master tx reset ds1921g sets memory address = [t15:t0] y y n n end of page? decision made by master decision made by ds1921g y n n end of memory? master rx "0" master rx crc-16 of command, address, data (1st pass); crc-16 of data (subsequent passes) ds1921g increments address counter n y ds1921g clears alarm timestamps and durations master tx reset? y ds1921g clears mission timestamp, mission samples counter, mission start delay, sample rate register 3ch clear memory n y ds1921g clears histogram memory ds1921g sets emclr = 0 ds1921g sets memclr = 1 emclr = 1? ds1921g sets emclr = 0 ds1921g sets memory address = [t15:t0] ds1921g increments address counter f0h read memory? n y y n y n master tx reset? end of memory? master rx ta1 [t7:t0], ta2 [t15:t8] master rx data byte from memory address master rx 00 byte figure 10b. memory/control function flowchart
ds1921g thermochron i button 24 ______________________________________________________________________________________ from figure 10b to figure 10b ds1921g sets tcb = 0 ds1921g sets tcb = 1 ds1921g performs a temperature conversion ds1921g sets emclr = 0 ds1921g starts temperature conversion process 44h convert temperature? n y y n y n mission in progress? master tx reset? ds1921g copies result to address 0211h y n master tx reset? temperature conversion process end of process figure 10c. memory/control function flowchart
read memory with crc [a5h] the read memory with crc command is used to read memory data that cannot be packetized, such as the register page and the data recorded by the device dur- ing a mission. the command works the same way as the simple read memory command, except for the 16- bit crc that the ds1921g generates and transmits fol- lowing the last data byte of a memory page. after having sent the command code of the read memory with crc command, the bus master sends a 2-byte address (ta1 = t[7:0], ta2 = t[15:8]) that indi- cates a starting byte location. with the subsequent read-data time slots, the master receives data from the ds1921g starting at the initial address and continues until the end of a 32-byte page is reached. at that point the bus master sends 16 additional read-data time slots and receives an inverted 16-bit crc. with subsequent read-data time slots the master receives data starting at the beginning of the next page followed again by the inverted crc for that page. this sequence continues until the bus master resets the device. with the initial pass through the read memory with crc command flow, the 16-bit crc value is the result of shifting the command byte into the cleared crc gen- erator followed by the two address bytes and the con- tents of the data memory. subsequent passes through the read memory with crc command flow generate a 16-bit crc that is the result of clearing the crc gener- ator and then shifting in the contents of the data memo- ry page. after the 16-bit crc of the last page is read, the bus master receives logical ?? from the ds1921g and inverted crc-16s at page boundaries until a reset pulse is issued. the read memory with crc command sequence can be ended at any point by issuing a reset pulse. clear memory [3ch] the clear memory command is used to clear the sample rate, mission start delay, mission timestamp, and mission samples counter in the register page and the temperature alarm memory and the temperature histogram memory. these memory areas must be cleared for the device to be set up for another mission. the clear memory command does not clear the data- log memory or the temperature and timer alarm flags in the status register. the rtc oscillator must be on and have counted at least 1s before issuing the command. for the clear memory command to function, the emclr bit in the control register must be set to 1, and the clear memory command must be issued with the very next access to the device? memory functions. issuing any other memory function command resets the emclr bit. the clear memory process takes 500?. when the command is completed the memclr bit in the status register reads 1 and the emclr bit is 0. convert temperature [44h] if a mission is not in progress (mip = 0), the convert temperature command can be issued to measure the current temperature of the device. the result of the tem- perature conversion can be found at memory address 211h in the register page. this command takes maxi- mum 90ms to complete. during this time the device remains fully accessible for memory/control and rom function commands. mission start and logging process the ds1921g does not use a special command to start a mission. instead, a mission is started by writing a nonzero value to the sample rate register using the copy scratchpad command. as shown in figure 11, a new mission can only be started if the previous mission has been stopped (mip = 0), the memory is cleared (memclr = 1), and the mission is enabled ( em = 0). if the new sample rate is different from zero, the value is copied to the sample rate register. at the same time the mip bit is set and the memclr bit is cleared to indi- cate that the device is on a mission. next, the mission start delay counter starts decrementing every minute until it is down to 0. now the ds1921g waits until the next minute boundary and starts the logging process, which as its first action copies the applicable rtc reg- isters to the mission timestamp register. stop mission the ds1921g does not have a special command to stop a mission. a mission can be stopped at any time by writing to any address in the range of 0200h to 0213h or by writing the mip bit of the status register at address 0214h to 0. either approach involves the use of the copy scratchpad command. there is no need for the mission start delay to expire before a mission can be stopped (see figure 11). memory access conflicts while a mission is in progress, a temperature sample is periodically taken and stored in the data-log, his- togram, and potential alarm memory. this ?nternal activity?has priority over a read memory command? or read memory with crc command? access to these pages. if a conflict occurs, the data read may be invalid, even if the crc value matches the data. to ensure that the data read is valid, it is recommended to first read the sip bit of the status register. if the sip bit is set, delay reading the data-log, histogram, and alarm memory until sip is 0. the interference is more likely to be seen with a high sample rate (one sample every ds1921g thermochron i button ______________________________________________________________________________________ 25
ds1921g thermochron i button 26 ______________________________________________________________________________________ ds1921g sets mip = 1; memclr = 0 ds1921g copies rtc to mission timestamp ds1921g sets mip = 0 ds1921g waits until next minute boundary ds1921g waits one sample period ds1921g logging process ds1921g waits until next minute boundary ds1921g copies new sample rate from scratchpad to sample rate register mip = 1? mip = 1? y n n new sample rate = 0? start delay counter = 0? n n n n em = 0? y n ro = 1? n y y n y memclr = 1? y ds1921g decrements start delay counter y mission start process ds1921g sets data-log address = 1000h ds1921g measures temperature ds1921g stores temperature at data-log address ds1921g increments data-log address ds1921g stores temperature at data-log address ds1921g increments lower 11 bits of data-log address ds1921g updates histogram, device samples counter, mission samples counter and alarm, if applicable mip = 1? data-log address = 1800h? y y logging process end of process end of process note: the mission start process is invoked when the copy scratchpad command is used to set a new sample rate by writing to the sampl e rate register at address 020dh. one minute after the start delay countdown is over, the logging process begins and the mission start process ends. figure 11. mission start and logging process
minute). since all mission samples occur on the sec- onds rollover (59 to 00), memory conflicts can be avoid- ed by first reading the rtc seconds counter. for example, if it takes 2s to read the data log, then avoid starting the memory read if the seconds counter is 58, 59, or 00. alternatively, one can read the affected mem- ory section twice and accept the data only if both read- ings match. in any case, when writing driver software, it is important to know about the possibility of interference and to take measures to work around it. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds1921g is a slave device. the bus master is typically a micro- controller. the discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transac- tions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three-state outputs. the 1-wire port of the ds1921g is open drain with an internal circuit equivalent to that shown in figure 12. a multidrop bus consists of a 1-wire bus with multiple slaves attached. at standard speed the 1-wire bus has a maximum data rate of 16.3kbps. the speed can be boosted to 142kbps by activating the overdrive mode. the ds1921g is not guaranteed to be fully compliant to the i button standard. its maximum data rate in standard speed is 15.4kbps and 125kbps in overdrive. the value of the pullup resistor primarily depends on the network size and load conditions. the ds1921g requires a pullup resistor of maximum 2.2k ? at any speed. the idle state for the 1-wire bus is high. if for any rea- son a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16? (overdrive speed) or more than 120? (standard speed), one or more devices on the bus may be reset. note that the ds1921g does not quite meet the full 16? maximum low time of the normal 1-wire bus overdrive timing. with the ds1921g the bus must be left low for no longer than 15? at overdrive speed to ensure that no ds1921g on the 1-wire bus performs a reset. the ds1921g communicates properly when used in conjunction with a ds2480b or ds2490 1-wire driver and adapters that are based on these driver chips. transaction sequence the protocol for accessing the ds1921g through the 1-wire port is as follows: initialization rom function command memory/control function command transaction/data ds1921g thermochron i button ______________________________________________________________________________________ 27 rx r pup i l v pup bus master open-drain port pin 100 ? mosfet tx rx tx data ds1921g 1-wire port rx = receive tx = transmit figure 12. hardware configuration
ds1921g initialization all transactions on the 1-wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master, followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds1921g is on the bus and is ready to operate. for more details, see the 1-wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands. all rom function commands are 8 bits long. a list of these commands follows (see the flowchart in figure 13). read rom [33h] this command allows the bus master to read the ds1921g? 8-bit family code, unique 48-bit serial num- ber and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the resultant fami- ly code and 48-bit serial number result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds1921g on a multidrop bus. only the ds1921g that exactly matches the 64-bit rom sequence responds to the memory function command. all other slaves wait for a reset pulse. this command can be used with a single device or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their registration numbers. by taking advantage of the wired-and property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. for each bit of the regis- tration number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the sec- ond slot, each slave device participating in the search outputs the complemented value of its registration num- ber bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participat- ing in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing which state to write, the bus master branches in the rom code tree. after one com- plete pass, the bus master knows the registration num- ber of a single device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. conditional search rom [ech] the conditional search rom command operates simi- larly to the search rom command except that only devices fulfilling the specified condition participate in the search. the condition is specified by the bit func- tions tas, ths, and tls in the control register, address 20eh. the conditional search rom provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a temperature leaving the tol- erance band. after each pass of the conditional search that successfully determined the 64-bit rom code for a specific device on the multidrop bus, that particular device can be individually accessed as if a match rom command had been issued, since all other devices have dropped out of the search process and are wait- ing for a reset pulse. for the conditional search, one can select any combi- nation of the three search conditions by writing the associated bit to a logical 1. these bits correspond directly to the flags in the status register of the device. if the flag in the status register reads 1 and the corre- sponding bit in the control register is a logical 1 too, the device responds to the conditional search rom command. if more than one bit search condition is selected, the first event that occurs makes the device respond to the conditional search rom command. skip rom [cch] this command can save time in a single-drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). thermochron i button 28 ______________________________________________________________________________________
ds1921g thermochron i button ______________________________________________________________________________________ 29 ds1921g tx presence pulse master tx reset pulse master tx rom function command ds1921g tx crc byte *to be transmitted or received at overdrive speed if od = 1. ** presence pulse is short if od = 1. ds1921g tx family code (1 byte) ds1921g tx serial number (6 bytes) od = 0 master tx bit 0 y short reset pulse? y y y y y y n 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? n ech conditional search command? n y master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y from memory/control functions flowchart (figure 10) to memory functions flowchart (figure 10) ds1921g tx bit 0 ds1921g tx bit 0 master tx bit 0 bit 1 match? bit 63 match? ds1921g tx bit 1 ds1921g tx bit 1 master tx bit 1 ds1921g tx bit 63 ds1921g tx bit 63 master tx bit 63 y bit 0 match? n n n y y ds1921g tx bit 0 ds1921g tx bit 0 master tx bit 0 condition met? n y bit 1 match? bit 63 match? ds1921g tx bit 1 ds1921g tx bit 1 master tx bit 1 ds1921g tx bit 63 ds1921g tx bit 63 master tx bit 63 y from figure 13b to figure 13b to figure 13b from figure 13b * * * * * * * * * * * * * * * * ** * * * * * * * figure 13a. rom functions flowchart
ds1921g thermochron i button 30 ______________________________________________________________________________________ master tx bit 0 od = 1 y n y 3ch overdrive- skip rom? n y cch skip rom command? y 69h overdrive- match rom? n n n n master tx bit 1 master tx bit 63 y y y bit 0 match? master tx reset pulse? bit 63 match? bit 1 match? n to figure 13a from figure 13a from figure 13a to figure 13a od = 1 ***always to be transmitted at overdrive speed. *** *** *** figure 13b. rom functions flowchart
overdrive-skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit rom code. unlike the normal skip rom command, the overdrive-skip rom command sets the ds1921g in the overdrive mode (od = 1). all communication following this com- mand must occur at overdrive speed until a reset pulse of minimum 480? duration resets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a match rom or search rom com- mand sequence. this speeds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive-skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired- and result). overdrive-match rom [69h] the overdrive-match rom command followed by a 64- bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds1921g on a multidrop bus and to simultaneously set it in over- drive mode. only the ds1921g that exactly matches the 64-bit rom sequence responds to the subsequent memory/control function command. slaves already in overdrive mode from a previous overdrive-skip or suc- cessful overdrive-match rom command remain in overdrive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480? duration. the overdrive-match rom command can be used with a single or multiple devices on the bus. 1-wire signaling the ds1921g requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and pres- ence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all these signals. the ds1921g can communicate at two different speeds: standard speed and overdrive speed. if not explicitly set into the overdrive mode, the ds1921g communicates at standard speed. while in overdrive mode, the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 14 as ?and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds1921g when determining a logical level, but not for triggering any events. the initialization sequence required to begin any com- munication with the ds1921g is shown in figure 14. a reset pulse followed by a presence pulse indicates the ds1921g is ready to receive data, given the correct rom and memory function command. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. ds1921g thermochron i button ______________________________________________________________________________________ 31 resistor master ds1921g t rstl t pdl t rsth t pdh master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp figure 14. intitialization procedure: reset and presence pulses
ds1921g a t rstl duration of 480? or longer exits the overdrive mode, returning the device to standard speed. if the ds1921g is in overdrive mode and t rstl is no longer than 80?, the device remains in overdrive mode. after the bus master has released the line, it goes into receive mode (rx). now the 1-wire bus is pulled to v pup through the pullup resistor or, in case of a ds2480b driver, through active circuitry. when the threshold v th is crossed, the ds1921g waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds1921g is ready for data communication. in a mixed population network, t rsth should be extend- ed to minimum 480? at standard speed and 48? at overdrive speed to accommodate other 1-wire devices. read/write time slots data communication with the ds1921g takes place in time slots that carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. the definitions of the write and read time slots are illustrated in figure 15. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below the threshold v tl , the ds1921g starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold after the write-one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. the voltage on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds1921g needs a recovery time t rec before it is ready for the next time slot. slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds1921g starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds1921g does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the inter- nal timing generator of the ds1921g on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for most reliable communication, t rl should be as short as permissible and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds1921g to get ready for the next time slot. crc generation there are two different types of crcs with the ds1921g. one crc is an 8-bit type and is stored in the most significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of the 64-bit rom and compare it to the value stored within the ds1921g to determine if the rom data has been received error-free. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (noninverted) form. it is computed at the factory and lasered into the rom. the other crc is a 16-bit type, generated according to the standardized crc-16 polynomial function x 16 + x 15 + x 2 + 1. this crc is used for error detection when reading data memory using the read memory with crc command and for fast verification of a data trans- fer when writing to or reading from the scratchpad. in contrast to the 8-bit crc, the 16-bit crc is always communicated in the inverted form. a crc-generator inside the ds1921g chip (figure 16) calculates a new 16-bit crc as shown in the command flowchart of figure 10. the bus master compares the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the crc error. with the initial pass through the read memory with crc flowchart, the 16-bit crc value is the result of shifting the command byte into the cleared crc gener- ator, followed by the 2 address bytes and the data bytes. subsequent passes through the read memory with crc flowchart generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the data bytes. with the write scratchpad command, the crc is gener- ated by first clearing the crc generator and then shift- ing in the command code, the target addresses ta1 and ta2, and all the data bytes. the ds1921g transmits this crc only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. the data can start at any location within the scratchpad. thermochron i button 32 ______________________________________________________________________________________
ds1921g thermochron i button ______________________________________________________________________________________ 33 resistor master resistor master resistor master ds1921g v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slot write-zero time slot read-data time slot figure 15. read/write timing diagram
ds1921g with the read scratchpad command, the crc is gen- erated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, the e/s byte, and the scratchpad data starting at the target address. the ds1921g transmits this crc only if the reading continues through the end of the scratchpad, regardless of the actual ending off- set. for more information on generating crc values refer to application note 27: understanding and using cyclic redundancy checks with maxim i button products. thermochron i button 34 ______________________________________________________________________________________ 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 16 + x 15 + x 2 + 1 input data crc output x 5 x 6 11th stage 12th stage 15th stage 14th stage 13th stage x 11 x 12 9th stage 10th stage x 9 x 10 x 13 x 14 x 7 16th stage x 16 x 15 x 8 figure 16. crc-16 hardware description and polynomial command-specific 1-wire communication protocol?egend symbol description rst 1-wire reset pulse generated by master pd 1-wire presence pulse generated by slave select command and data to satisfy the rom function protocol (skip rom, search rom, etc.) ws command: write scratchpad rs command: read scratchpad cps command: copy scratchpad rm command: read memory rmc command: read memory with crc cm command: clear memory ct command: convert temperature ta target address ta1, ta2 ta-e/s target address ta1, ta2 with e/s byte transfer of as many data bytes as are needed to reach the scratchpad offset 1fh transfer of as many data bytes as are needed to reach the end of a memory page transfer of as many data bytes as are needed to reach the end of the data-log memory
command-specific 1-wire communication protocol?olor codes ds1921g thermochron i button ______________________________________________________________________________________ 35 master-to-slave slave-to-master ff loop rst cps rst ws rs ta crc-16 ff loop ff loop 00 loop crc-16 ta-e/s ta-e/s cps ta-e/s ws ta ta write scratchpad, reaching the end of the scratchpad pd pd select rst write scratchpad, not reaching the end of the scratchpad pd select rst read scratchpad pd select aa loop rst rm copy scratchpad (success) pd select rst copy scratchpad (invalid ta-e/s) pd select rst read memory (success) pd select 00 loop ta rm rst read memory (invalid address) pd select reading reserved pages 20 through 63 or 68 through 127 or pages 192 and higher (beyond data-log memory) results in 00h bytes. command-specific 1-wire communication protocol?egend (continued) symbol description <00 to eop> transfer of as many 00h bytes as are needed to reach a memory page boundary <32 bytes> transfer of 32 bytes transfer of an undetermined amount of data crc-16 transfer of an inverted crc-16 ff loop indefinite loop where the master reads ffh bytes aa loop indefinite loop where the master reads aah bytes 00 loop indefinite loop where the master reads 00h bytes 1-wire communication examples
ds1921g mission example: prepare and start a new mission assumption: the previous mission has ended. to end an ongoing mission write the mip bit in the status regis- ter to 0. the preparation of a ds1921g for a mission including the start of the mission requires up to four steps: step 1: set the rtc (if it needs to be adjusted). step 2: clear the data of the previous mission. step 3: set the search condition and mission start delay and clear the alarm flags. step 4: set the temperature alarms and write the sample rate to start the mission. thermochron i button 36 ______________________________________________________________________________________ 1-wire communication examples (continued) ff loop ff loop cm rst clear memory pd select to verify success, read the status register at address 0214h. if memclr is 1, the command was executed successfully. to read the result and to verify success, read the addresses 0211h (result) and the device samples counter at address 021dh to 021fh. if the count has incremented, the command was executed successfully. ct rst convert temperature pd select <32 bytes> crc-16 crc-16 loop rmc ta rst read memory with crc (success) pd select the ?2 bytes?are either valid page data or 00h bytes when reading reserved pages 20 through 63 or 68 through 127 or pages 192 and higher (beyond data-log memory). <32 bytes> <00 to eop> crc-16 crc-16 loop rmc ta rst read memory with crc (invalid address) pd select the ?2 bytes?are all 00h.
step 1: set the rtc let the actual time be 15:30:00 hours on monday, the 1st of april in 2002. this results in the following data to be writ- ten to the rtc registers: with only a single ds1921g connected to the bus master, the communication of step 1 is as follows: ds1921g thermochron i button ______________________________________________________________________________________ 37 address 200h 201h 202h 203h 204h 205h 206h data 00h 30h 15h 01h 81h 04h 02h master mode data (lsb first) comments tx (reset) reset pulse (480s to 960s) rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 00h ta1, beginning offset = 00h tx 02h ta2, address = 02 00h tx <7 data bytes> write 7 bytes of data to scratchpad tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 00h read ta1, beginning offset = 00h rx 02h read ta2, address = 02 00h rx 06h read e/s, ending offset = 6h, flags = 0h rx <7 data bytes> read scratchpad data and verify tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 00h ta1 tx 02h ta2 tx 06h e/s (authorization code) tx (reset) reset pulse rx (presence) presence pulse
ds1921g step 2: clear the data of the previous mission set the emclr bit to 1, enable the rtc, and then execute the clear memory command. the rtc oscillator must be stable before the clear memory command is issued. wait 500? after issuing the clear memory command before proceeding to step 3. this results in the following data to be written to the status register: with only a single ds1921g connected to the bus master, the communication of step 2 is as follows: thermochron i button 38 ______________________________________________________________________________________ address 20eh data 40h master mode data (lsb first) comments tx (reset) reset pulse (480s to 960s) rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 0eh ta1, beginning offset = 0eh tx 02h ta2, address = 02 0eh tx 40h write status byte to scratchpad tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 0eh read ta1, beginning offset = 0eh rx 02h read ta2, address = 02 0eh rx 0eh read e/s, ending offset = 0eh, flags = 0h rx 40h read scratchpad data and verify tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 0eh ta1 tx 02h ta2 tx 0eh e/s (authorization code) tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 3ch issue clear memory command tx (reset) reset pulse rx (presence) presence pulse
step 3: set the search condition and mission start delay and clear the alarm flags in this example, the rollover is disabled and the search condition is set for a high temperature only. the mission is to start with a delay of 90min (005ah) and the alarm flags tlf, thf, and taf are cleared. this results in the follow- ing data to be written to the special function registers: with only a single ds1921g connected to the bus master, the communication of step 3 is as follows: ds1921g thermochron i button ______________________________________________________________________________________ 39 address 20eh 20fh 210h 211h 212h 213h 214h data 02h 00h* 00h* 00h* 5ah 00h 00h master mode data (lsb first) comments tx (reset) reset pulse (480s to 960s) rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 0eh ta1, beginning offset = 0eh tx 02h ta2, address = 02 0eh tx <7 data bytes> write 7 bytes of data to scratchpad tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 0eh read ta1, beginning offset = 0eh rx 02h read ta2, address = 02 0eh rx 14h read e/s, ending offset = 14h, flags = 0h rx <7 data bytes> read scratchpad data and verify tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 0eh ta1 tx 02h ta2 tx 13h e/s (authorization code) tx (reset) reset pulse rx (presence) presence pulse * writing through address locations 20fh to 211h is faster than accessing the mission start delay register in a separate cycle. t he write attempt has no effect on the contents of these registers.
ds1921g step 4: set the temperature alarms and write the sample rate to start the mission in this example, the temperature alarms are set to -5? for the low temperature threshold and 0? for the high tem- perature threshold. the sample rate is once every 10min, allowing the mission to last up to 14 days. this results in the following data to be written to the special function registers: with only a single ds1921g connected to the bus master, the communication of step 4 is as follows: thermochron i button 40 ______________________________________________________________________________________ address 20bh 20ch 20dh data 46h 50h 0ah master mode data (lsb first) comments tx (reset) reset pulse (480s to 960s) rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 0bh ta1, beginning offset = 0bh tx 02h ta2, address = 02 0bh tx <3 data bytes> write 3 bytes of data to scratchpad tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 0bh read ta1, beginning offset = 0bh rx 02h read ta2, address = 02 0bh rx 0dh read e/s, ending offset = 0dh, flags = 0h rx <3 data bytes> read scratchpad data and verify tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 0bh ta1 tx 02h ta2 tx 0dh e/s (authorization code) tx (reset) reset pulse rx (presence) presence pulse if step 4 is successful, the mip bit in the status register is 1, the memclr bit is 0, and the mission start delay counts down.
ds1921g thermochron i button ______________________________________________________________________________________ 41 89 21 000000fbc52b 1-wire thermochrom i b u t t o n . c o m y y w w z z z d s 1 9 2 1 g # f 5 0 16.25mm 5.89mm 0.51mm 17.35mm branding gnd note: the DS1921G-F5N# has a #f5n suffix. io pin configuration package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. f5 i button ib#5cp 21-0266
ds1921g thermochron i button maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 42 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed added bullet water resistant or waterproof if placed inside ds9107 ibutton capsule (exceeds water resistant 3 atm requirements) deleted application pending from ul bullet and safety statement 120407 added text to detailed description section: note that the initial sealing level of ds1921g achieves ip56. aging and use conditions can degrade the integrity of the seal over time, so for applications with significant exposure to liquids, sprays, or other similar environments, it is recommended to place the thermochron in the ds9107 i button capsule. the ds9107 provides a watertight enclosure that has been rated to ip68 (see www.maxim-ic.com/an4126 ) 1, 2 4/09 created newer template-style data sheet all 4/10 overdrive specifications for t rstl , t pdl , and t w0l split into range v pup > 4.5v and full range. new values for the full range 2C4 4/11 updated ul certificate reference; deleted from the t w1l specification in the electrical characteristics table; applied note 13 to the t w0l specification in the electrical characteristics table; added more details to electrical characteristics table notes 7, 13, and 14 1, 3, 4 9/11 DS1921G-F5N# part number added to the ordering information ; branding information updated in the pin configuration 1, 41 3/12 added terminology updates for consistency with similar products; added more details to the parasite power section 1, 7, 8, 9, 14

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